25 search results - page 5 / 5 » Standby Leakage Power Reduction Technique for Nanoscale CMOS... |
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
CODES
2008
IEEE
13 years 6 months ago
2008
IEEE
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
DATE
2008
IEEE
13 years 10 months ago
2008
IEEE
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
ISLPED
2006
ACM
13 years 10 months ago
2006
ACM
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...