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» Standby Leakage Power Reduction Technique for Nanoscale CMOS...
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ICCD
2007
IEEE
322views Hardware» more  ICCD 2007»
10 years 10 months ago
Voltage drop reduction for on-chip power delivery considering leakage current variations
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
CODES
2008
IEEE
10 years 3 months ago
Design and defect tolerance beyond CMOS
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. ...
DATE
2008
IEEE
132views Hardware» more  DATE 2008»
10 years 7 months ago
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
Ehsan Pakbaznia, Massoud Pedram
VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
11 years 1 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
10 years 7 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
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