Sciweavers

1249 search results - page 2 / 250
» State Machine Modeling: From Synch States to Synchronized St...
Sort
View
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
13 years 10 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
FIW
2009
163views Communications» more  FIW 2009»
13 years 4 months ago
Detecting policy conflicts by model checking UML state machines
Policies are convenient means to modify system behaviour at run-time. Nowadays, policies are created in great numbers by different actors, ranging from system administrators to lay...
Maurice H. ter Beek, Stefania Gnesi, Carlo Montang...
ARVLSI
1995
IEEE
179views VLSI» more  ARVLSI 1995»
13 years 9 months ago
Algorithms for the optimal state assignment of asynchronous state machines
This paper presents a method for the optimal state assignment of asynchronous state machines. Unlike state assignment for synchronous state machines, state codes must be chosen ca...
Robert M. Fuhrer, Bill Lin, Steven M. Nowick
ICWE
2011
Springer
12 years 9 months ago
Formal Modeling of RESTful Systems Using Finite-State Machines
Representational State Transfer (REST), as an architectural style for distributed hypermedia systems, enables scalable operation of the World Wide Web (WWW) and is the foundation f...
Ivan Zuzak, Ivan Budiselic, Goran Delac
ACL
2010
13 years 4 months ago
cdec: A Decoder, Alignment, and Learning Framework for Finite-State and Context-Free Translation Models
We present cdec, an open source framework for decoding, aligning with, and training a number of statistical machine translation models, including word-based models, phrase-based m...
Chris Dyer, Adam Lopez, Juri Ganitkevitch, Jonatha...