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DAC
2004
ACM
14 years 5 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 4 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
DAC
2008
ACM
13 years 6 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
VLSID
2008
IEEE
153views VLSI» more  VLSID 2008»
14 years 4 months ago
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation
Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. Howeve...
Yuanlin Lu, Vishwani D. Agrawal
ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
14 years 1 months ago
Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation
— As the technology scales into 90nm and below, process-induced variations become more pronounced. In this paper, we propose an efficient stochastic method for analyzing the vol...
Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan