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» Statistical technology mapping for parametric yield
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ICCAD
2005
IEEE
87views Hardware» more  ICCAD 2005»
14 years 2 months ago
Statistical technology mapping for parametric yield
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
Ashish Kumar Singh, Murari Mani, Michael Orshansky
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
13 years 11 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
13 years 9 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 2 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
ISBI
2009
IEEE
14 years 4 days ago
A Non-Parametric Approach to Automatic Change Detection in MRI Images of the Brain
We present a novel approach to change detection between two brain MRI scans (reference and target.) The proposed method uses a single modality to find subtle changes; and does no...
Hae Jong Seo, Peyman Milanfar