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» Steiner network construction for timing critical nets
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DAC
2006
ACM
10 years 2 months ago
Steiner network construction for timing critical nets
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open f...
Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
10 years 11 months ago
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...
Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun...
ISPD
2003
ACM
88views Hardware» more  ISPD 2003»
10 years 3 months ago
Porosity aware buffered steiner tree construction
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jia...
TCAD
2008
128views more  TCAD 2008»
9 years 10 months ago
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (...
Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen C...
GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
10 years 15 days ago
Resource-constrained timing-driven link insertion for critical delay reduction
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
Jin-Tai Yan, Zhi-Wei Chen
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