13 search results - page 1 / 3 » Stochastic Optimization Approach to Transistor Sizing for CM... |
DAC
1994
ACM
13 years 8 months ago
1994
ACM
A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with ...
DATE
2008
IEEE
13 years 10 months ago
2008
IEEE
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
ISLPED
1999
ACM
13 years 8 months ago
1999
ACM
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
GLVLSI
2007
IEEE
13 years 10 months ago
2007
IEEE
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...
VLSID
1999
IEEE
13 years 8 months ago
1999
IEEE
A new approach for CMOS op-amp circuit synthesis has proposed here. The approach is based on the observation that the rst order behavior of a MOS transistor in the saturation regi...