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» Storage coding for wear leveling in flash memories
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DAC
2006
ACM
14 years 6 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
LCPC
2007
Springer
13 years 11 months ago
Revisiting SIMD Programming
Massively parallel SIMD array architectures are making their way into embedded processors. In these architectures, a number of identical processing elements having small private st...
Anton Lokhmotov, Benedict R. Gaster, Alan Mycroft,...
SOCIALCOM
2010
13 years 1 hour ago
A Multi-factor Approach to Securing Software on Client Computing Platforms
Protecting the integrity of software platforms, especially in unmanaged consumer computing systems is a difficult problem. Attackers may attempt to execute buffer overflow attacks ...
Raghunathan Srinivasan, Vivek Iyer, Amit Kanitkar,...
DSN
2006
IEEE
13 years 9 months ago
Efficient High Hamming Distance CRCs for Embedded Networks
Cyclic redundancy codes (CRCs) are widely used in network transmission and data storage applications because they provide better error detection than lighter weight checksum techn...
Justin Ray, Philip Koopman
MBEES
2010
13 years 6 months ago
Towards Architectural Programming of Embedded Systems
: Integrating architectural elements with a modern programming language is essential to ensure a smooth combination of architectural design and programming. In this position statem...
Arne Haber, Jan Oliver Ringert, Bernhard Rumpe