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MTV
2007
IEEE
118views Hardware» more  MTV 2007»
14 years 5 months ago
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
Wang-Dauh Tseng, Lung-Jen Lee
ICCAD
1999
IEEE
67views Hardware» more  ICCAD 1999»
14 years 3 months ago
Realizable reduction for RC interconnect circuits
Interconnect reduction is an important step in the design and analysis of complex interconnects found in present-day integrated circuits. This paper presents techniques for obtain...
Anirudh Devgan, Peter R. O'Brien
CSR
2009
Springer
14 years 5 months ago
Depth Reduction for Circuits with a Single Layer of Modular Counting Gates
We consider the class of constant depth AND/OR circuits augmented with a layer of modular counting gates at the bottom layer, i.e AC0 ◦MODm circuits. We show that the following ...
Kristoffer Arnsfelt Hansen
DFT
2003
IEEE
106views VLSI» more  DFT 2003»
14 years 4 months ago
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits
Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This papers pr...
Atul Maheshwari, Israel Koren, Wayne Burleson
ICCAD
1995
IEEE
108views Hardware» more  ICCAD 1995»
14 years 2 months ago
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
This paper presents a linear time algorithm to reduce a large RC interconnect network into subnetworks which are approximated with lower order equivalent RC circuits. The number o...
Haifang Liao, Wayne Wei-Ming Dai