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» Study of Floating Fill Impact on Interconnect Capacitance
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ISQED
2006
IEEE
89views Hardware» more  ISQED 2006»
13 years 10 months ago
Study of Floating Fill Impact on Interconnect Capacitance
It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating ...
Andrew B. Kahng, Kambiz Samadi, Puneet Sharma
VLSID
2007
IEEE
103views VLSI» more  VLSID 2007»
14 years 4 months ago
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
Abstract-- This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variation...
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopala...
DAC
2003
ACM
14 years 5 months ago
Performance-impact limited area fill synthesis
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
Yu Chen, Puneet Gupta, Andrew B. Kahng
ICCD
2006
IEEE
94views Hardware» more  ICCD 2006»
14 years 1 months ago
Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward I
Abstract— Capacitive and inductive crosstalk noises are expected to be more serious in advanced technologies. However, capacitive and inductive crosstalk noises in the future hav...
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoy...