4 search results - page 1 / 1 » Substrate Noise Reduction Based On Noise Aware Cell Design |
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
— A substrate biasing methodology is introduced based on modifying standard cells by inserting dedicated substrate contacts in those cells behaving as aggressive digital noise ge...
TVLSI
2008
13 years 4 months ago
2008
Abstract--In this paper, we introduce a novel substrate noise estimation technique during early floorplanning for mixed signal system-on-chip (SOC), based on block preference direc...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...