Sciweavers

3 search results - page 1 / 1
» Subthreshold logical effort: a systematic framework for opti...
Sort
View
DAC
2006
ACM
14 years 5 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
TVLSI
2008
74views more  TVLSI 2008»
13 years 4 months ago
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
ICCD
2008
IEEE
165views Hardware» more  ICCD 2008»
14 years 1 months ago
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...