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HPCA
2008
IEEE
14 years 6 months ago
Supporting highly-decoupled thread-level redundancy for parallel programs
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
M. Wasiur Rashid, Michael C. Huang
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
13 years 12 months ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
ICMCS
2006
IEEE
152views Multimedia» more  ICMCS 2006»
13 years 11 months ago
Muli-Issue Multi-Threaded Stream Processor
The MISP Processor is a programmable media processor which supports multi-issuing, multi-threading and stream processing techniques. MISP executes applications that have been mapp...
Somayeh Sardashti, Hamid Reza Ghasemi, Omid Fatemi
ICS
1998
Tsinghua U.
13 years 10 months ago
High-level Management of Communication Schedules in HPF-like Languages
The goal of High Performance Fortran (HPF) is to "address the problems of writing data parallel programs where the distribution of data affects performance", providing t...
Siegfried Benkner, Piyush Mehrotra, John Van Rosen...
ASPLOS
2010
ACM
14 years 15 days ago
Speculative parallelization using software multi-threaded transactions
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B....