199 search results - page 1 / 40 » Switching Activity Minimization in Combinational Logic Desig... |
CSREAESA
2004
13 years 5 months ago
2004
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
CSREAESA
2003
13 years 5 months ago
2003
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
CEC
2005
IEEE
13 years 10 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...