50 search results - page 1 / 10 » Synchronization Processor Synthesis for Latency Insensitive ... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carlon...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...