7 search results - page 2 / 2 » Synchronization Verification in System-Level Design with ILP... |
ASYNC
1997
IEEE
13 years 8 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...