95 search results - page 1 / 19 » Synchronous Interlocked Pipelines |
ASYNC
2002
IEEE
13 years 10 months ago
2002
IEEE
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
MICRO
1994
IEEE
13 years 9 months ago
1994
IEEE
We examine two pipeline structures which are employed in commercial microprocessors. The first is the load-use interlock (LUI) pipeline, which employs an interlock to ensure corre...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
The interlock and forwarding logic is considered the tricky part of a fully-featured pipelined microprocessor and especially debugging these parts delays the hardware design proce...
TVLSI
2011
13 years 2 days ago
2011
—Communication costs, which have the potential to throttle design performance as scaling continues, are mathematically modeled and compared for various pipeline methodologies. Fi...
HPCA
1995
IEEE
13 years 8 months ago
1995
IEEE
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...