47 search results - page 1 / 10 » Synchronous Transfer Architecture (STA) |
SAMOS
2004
Springer
13 years 9 months ago
2004
Springer
This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and ...
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
ASPDAC
2011
ACM
12 years 7 months ago
2011
ACM
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
DAC
2011
ACM
12 years 4 months ago
2011
ACM
Just as electronic systems implement computation in terms of voltage (energy per unit charge), molecular systems compute in terms of chemical concentrations (molecules per unit vo...
CF
2010
ACM
13 years 9 months ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...