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» Synthesis of Efficient Linear Test Pattern Generators
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EVOW
2001
Springer
13 years 8 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
DAC
2003
ACM
13 years 8 months ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 8 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
13 years 10 months ago
Generation of compact test sets with high defect coverage
Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide hi...
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
ITC
1995
IEEE
104views Hardware» more  ITC 1995»
13 years 7 months ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey