25 search results - page 2 / 5 » Synthesis of Instruction Sets for Pipelined Microprocessors |
APCSAC
2001
IEEE
13 years 8 months ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
MICRO
1993
IEEE
13 years 8 months ago
1993
IEEE
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
DAC
2004
ACM
13 years 9 months ago
2004
ACM
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
ISCA
1998
IEEE
13 years 8 months ago
1998
IEEE
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...
GLVLSI
1998
IEEE
13 years 8 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...