25 search results - page 5 / 5 » Synthesis of Instruction Sets for Pipelined Microprocessors |
ISSS
2002
IEEE
13 years 9 months ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
ISPASS
2006
IEEE
13 years 10 months ago
2006
IEEE
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
TJS
2002
13 years 4 months ago
2002
Historically, compilers have operated by applying a fixed set of optimizations in a predetermined order. We call such an ordered list of optimizations a compilation sequence. This...
DAC
1999
ACM
13 years 8 months ago
1999
ACM
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...