78 search results - page 1 / 16 » System level power and performance modeling of GALS point-to... |
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
ASYNC
2002
IEEE
13 years 9 months ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
This paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. More precisely, we introduce an analytical approach based on ...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Simila...