88 search results - page 3 / 18 » System-Level Modeling of Dynamically Reconfigurable Hardware... |
TC
2010
13 years 11 days ago
2010
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
AICCSA
2007
IEEE
14 years 2 hour ago
2007
IEEE
This paper discusses an approach for solving combinatorial problems by combining software and dynamically reconfigurable hardware (configware). The suggested technique avoids inst...
DATE
2008
IEEE
14 years 3 days ago
2008
IEEE
Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Simila...
FCCM
2006
IEEE
13 years 9 months ago
2006
IEEE
With advances in reconfigurable hardware, especially field-programmable gate arrays (FPGAs), it has become possible to use reconfigurable hardware to accelerate complex applicatio...