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DATE
2009
IEEE
153views Hardware» more  DATE 2009»
13 years 11 months ago
TRAM: A tool for Temperature and Reliability Aware Memory Design
— Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system’s power dissipation, area and reliability. In th...
Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurd...
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
13 years 10 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Thermal aware cell-based full-chip electromigration reliability analysis
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
IJES
2007
92views more  IJES 2007»
13 years 4 months ago
Exploring temperature-aware design in low-power MPSoCs
: The power density in high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating ‘hot spotsâ€...
Giacomo Paci, Francesco Poletti, Luca Benini, Paul...
ISLPED
2010
ACM
202views Hardware» more  ISLPED 2010»
13 years 4 months ago
MODEST: a model for energy estimation under spatio-temporal variability
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...