30 search results - page 2 / 6 » Tableaux and Model Checking for Memory Logics |
ENTCS
2010
13 years 2 months ago
2010
We present MLSolver, a tool for solving the satisfiability and validity problems for modal fixpoint logics. The underlying technique is based on characterisations of satisfiabilit...
ATAL
2010
Springer
13 years 5 months ago
2010
Springer
ATL+ is a variant of alternating-time temporal logic that does not have the expressive power of full ATL , but still allows for expressing some natural properties of agents. It ha...
DAC
1998
ACM
14 years 6 months ago
1998
ACM
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
RTSS
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents an on-the-fly and symbolic algorithm for checking whether a timed automaton satisfies a formula of a timed temporal logic which is more expressive than TCTL....
DAC
2008
ACM
14 years 6 months ago
2008
ACM
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...