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DATE
2006
IEEE
171views Hardware» more  DATE 2006»
13 years 10 months ago
4G applications, architectures, design methodology and tools for MPSoC
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the n...
GLOBECOM
2008
IEEE
13 years 4 months ago
Power Efficient Throughput Maximization in Multi-Hop Wireless Networks
Abstract-- We study the problem of total throughput maximization in arbitrary multi-hop wireless networks, with constraints on the total power usage (denoted by PETM), when nodes h...
Deepti Chafekar, V. S. Anil Kumar, Madhav V. Marat...
INTEGRATION
2008
127views more  INTEGRATION 2008»
13 years 2 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
SIGCOMM
2010
ACM
13 years 4 months ago
Design and implementation of an "approximate" communication system for wireless media applications
All practical wireless communication systems are prone to errors. At the symbol level such wireless errors have a well-defined structure: when a receiver decodes a symbol erroneou...
Sayandeep Sen, Syed Gilani, Shreesha Srinath, Step...