54 search results - page 2 / 11 » Teaching Hardware Description and Verification |
CHARME
2001
Springer
13 years 8 months ago
2001
Springer
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The ...
FPL
1999
Springer
13 years 9 months ago
1999
Springer
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
DSD
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
RSP
1998
IEEE
13 years 8 months ago
1998
IEEE
A technique to include virtual prototyping in the design cycle of complex digital modem ASICs is presented. It is innovating by using the same behavioral description for both the ...