54 search results - page 3 / 11 » Teaching Hardware Description and Verification |
DAC
2006
ACM
13 years 12 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DATE
2006
IEEE
14 years 1 days ago
2006
IEEE
Most hardware description languages do not enforce determinacy, meaning that they may yield races. Race conditions pose a problem for the implementation, verification, and validat...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
ASIAN
2009
Springer
13 years 7 months ago
2009
Springer
Abstract. Clever algorithm design is sometimes superseded by simple encodings into logic. We apply this motto to a few case studies in the formal verification of security propertie...