2 search results - page 1 / 1 » Techniques for Reducing Read Latency of Core Bus Wrappers |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...