10 search results - page 1 / 2 » Technology Mapping for Area Optimized Quasi Delay Insensitiv... |
VLSI
2005
Springer
13 years 9 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
In this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of mini...
FPGA
2006
ACM
13 years 8 months ago
2006
ACM
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...