This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...
—The stationarity hypothesis is largely and implicitly assumed when designing classifiers (especially those for industrial applications) but it does not generally hold in practic...
Scaling of electronics technology has brought us to a pivotal point in the design of computational devices. Technology scaling favours transistors over wires which has led us into...
The high random and sequential I/O requirements of contemplated workloads could serve as impetus to move faster towards storage-class memory (SCM), a technology that will blur the...
Evangelos Eleftheriou, Robert Haas, Jens Jelitto, ...