2 search results - page 1 / 1 » Technology-based Architectural Analysis of Operand Bypass Ne... |
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. In this paper, a distributed re...