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DAC
2006
ACM
14 years 6 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
DAC
2006
ACM
13 years 7 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
CF
2009
ACM
13 years 11 months ago
Wave field synthesis for 3D audio: architectural prospectives
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, G...
DATE
2008
IEEE
99views Hardware» more  DATE 2008»
13 years 11 months ago
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures
As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can serious...
Fabrizio Mulas, Michele Pittau, Marco Buttu, Salva...
DAC
2010
ACM
13 years 9 months ago
Cost-driven 3D integration with interconnect layers
The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a p...
Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna ...