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» Tera-scale computing and interconnect challenges
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VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
13 years 10 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
ISLPED
2005
ACM
93views Hardware» more  ISLPED 2005»
13 years 10 months ago
Power-aware code scheduling for clusters of active disks
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
DAGSTUHL
2006
13 years 6 months ago
Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
Douglas L. Maskell, Timothy F. Oliver
CAL
2007
13 years 4 months ago
Logic-Based Distributed Routing for NoCs
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
José Flich, José Duato
MOBISYS
2009
ACM
14 years 5 months ago
Point&Connect: intention-based device pairing for mobile phone users
Point&Connect (P&C) offers an intuitive and resilient device pairing solution on standard mobile phones. Its operation follows the simple sequence of point-and-connect: wh...
Chunyi Peng, Guobin Shen, Yongguang Zhang, Songwu ...