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» Test Compression for Dynamically Reconfigurable Processors
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RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
13 years 9 months ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
13 years 9 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
SP
2002
IEEE
109views Security Privacy» more  SP 2002»
13 years 4 months ago
Scalable atomistic simulation algorithms for materials research
A suite of scalable atomistic simulation programs has been developed for materials research based on space-time multiresolution algorithms. Design and analysis of parallel algorit...
Aiichiro Nakano, Rajiv K. Kalia, Priya Vashishta, ...