Sciweavers

5 search results - page 1 / 1
» Test Consideration for Nanometer-Scale CMOS Circuits
Sort
View
DT
2006
109views more  DT 2006»
13 years 4 months ago
Test Consideration for Nanometer-Scale CMOS Circuits
The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing de...
Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
TVLSI
2008
99views more  TVLSI 2008»
13 years 4 months ago
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
Sheng-Chih Lin, Kaustav Banerjee
ARVLSI
2001
IEEE
305views VLSI» more  ARVLSI 2001»
13 years 8 months ago
Logic Design Considerations for 0.5-Volt CMOS
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
K. Joseph Hass, Jack Venbrux, Prakash Bhatia
ITC
1989
IEEE
82views Hardware» more  ITC 1989»
13 years 8 months ago
CMOS IC Stuck-Open Fault Electrical Effects and Design Considerations
- The electrical effects of CMOS IC physical defects that caused stuck-openfaults are evaluated, including their voltage levels, quiescent power supply current (IDDQ), transient re...
Jerry M. Soden, R. Keith Treece, Michael R. Taylor...
EH
2004
IEEE
115views Hardware» more  EH 2004»
13 years 8 months ago
Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip
The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog converter (DAC) with a voltage mode output by hardware evolution. Thereby a Field Progr...
Jörg Langeheine, Karlheinz Meier, Johannes Sc...