8 search results - page 1 / 2 » Test Point Insertion: Scan Paths through Combinational Logic |
DAC
1996
ACM
13 years 8 months ago
1996
ACM
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
TCAD
1998
13 years 4 months ago
1998
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
Functional scan chains are scan chains that have scan paths through a circuit's functional logic and flip-flops. Establishing functional scan paths by test point insertion (T...
ATS
2005
IEEE
13 years 10 months ago
2005
IEEE
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...