Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce b...