5 search results - page 1 / 1 » Test application time and volume compression through seed ov... |
DAC
2003
ACM
13 years 9 months ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
DFT
2002
IEEE
13 years 9 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
DFT
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...