26 search results - page 1 / 6 » Testing Configurable LUT-Based FPGAs |
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM...
JISE
2000
13 years 4 months ago
2000
IAJIT
2010
13 years 3 months ago
2010
: A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller in programmable logic devices, and field programmable gate arra...