Sciweavers

6 search results - page 1 / 2
» Testing High-Speed SoCs Using Low-Speed ATEs
Sort
View
VTS
2002
IEEE
107views Hardware» more  VTS 2002»
13 years 8 months ago
Testing High-Speed SoCs Using Low-Speed ATEs
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate...
Mehrdad Nourani, James Chin
ET
2002
85views more  ET 2002»
13 years 3 months ago
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
Mehrdad Nourani, Amir Attarha
ICCD
2003
IEEE
89views Hardware» more  ICCD 2003»
13 years 9 months ago
Power-Time Tradeoff in Test Scheduling for SoCs
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
Mehrdad Nourani, James Chin
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
13 years 7 months ago
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores
This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator appl...
Mounir Benabdenbi, Alain Greiner, François ...
ISVLSI
2008
IEEE
152views VLSI» more  ISVLSI 2008»
13 years 10 months ago
Improving the Test of NoC-Based SoCs with Help of Compression Schemes
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is b...
Julien Dalmasso, Érika F. Cota, Marie-Lise ...