Sciweavers

217 search results - page 1 / 44
» The Block-Based Trace Cache
Sort
View
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
13 years 9 months ago
The Block-Based Trace Cache
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
Bryan Black, Bohuslav Rychlik, John Paul Shen
VIS
2006
IEEE
101views Visualization» more  VIS 2006»
14 years 6 months ago
Mesh Layouts for Block-Based Caches
Sung-Eui Yoon, Peter Lindstrom
CODES
2007
IEEE
13 years 11 months ago
Performance improvement of block based NAND flash translation layer
With growing capacities of flash memories, an efficient layer to manage read and write access to flash is required. NFTL is a widely used block based flash translation layer de...
Siddharth Choudhuri, Tony Givargis
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
13 years 9 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
ISCA
2000
IEEE
92views Hardware» more  ISCA 2000»
13 years 9 months ago
Trace preconstruction
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
Quinn Jacobson, James E. Smith