68 search results - page 11 / 14 » The Impact of Memory Hierarchies on Cluster Computing |
HPDC
2009
IEEE
14 years 16 days ago
2009
IEEE
Long running High Performance Computing (HPC) applications at scale must be able to tolerate inevitable faults if they are to harness current and future HPC systems. Message Passi...
SIGMETRICS
2009
ACM
14 years 8 days ago
2009
ACM
Errors in dynamic random access memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and...
IPPS
2009
IEEE
14 years 13 days ago
2009
IEEE
PDE solvers using Adaptive Mesh Refinement on block structured grids are some of the most challenging applications to adapt to massively parallel computing environments. We descr...
IPPS
2003
IEEE
13 years 11 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
IEEEPACT
2002
IEEE
13 years 10 months ago
2002
IEEE
Data parallel compilers have long aimed to equal the performance of carefully hand-optimized parallel codes. For tightly-coupled applications based on line sweeps, this goal has b...