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» The Impact of Resource Partitioning on SMT Processors
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CGO
2004
IEEE
13 years 9 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
CASES
2003
ACM
13 years 10 months ago
Programming challenges in network processor deployment
Programming multi-processor ASIPs, such as network processors, remains an art due to the wide variety of architectures and due to little support for exploring different implement...
Chidamber Kulkarni, Matthias Gries, Christian Saue...
IEEEPACT
2007
IEEE
13 years 11 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
13 years 9 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
ANCS
2005
ACM
13 years 10 months ago
Design considerations for network processor operating systems
Network processors (NPs) promise a flexible, programmable packet processing infrastructure for network systems. To make full use of the capabilities of network processors, it is ...
Tilman Wolf, Ning Weng, Chia-Hui Tai