202 search results - page 2 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
ISCA
2012
IEEE
11 years 7 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
ICPADS
1998
IEEE
13 years 9 months ago
1998
IEEE
Java-Web Computing paradigm changed Internet into computing environment. For Java-Web Computing and many Java applications, a new Java processor, called simultaneous multithreaded...
ASPLOS
2006
ACM
13 years 8 months ago
2006
ACM
Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around t...
ISCA
1996
IEEE
13 years 9 months ago
1996
IEEE
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...