202 search results - page 40 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
RTSS
2006
IEEE
13 years 11 months ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
APCSAC
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, a runtime performance projection model for dynamic power management is proposed. The model is built as a first-order linear equation using a linear regression model....
JSA
2000
13 years 5 months ago
2000
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
ISPDC
2010
IEEE
13 years 3 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
SC
2009
ACM
14 years 2 days ago
2009
ACM
The availability of large quantities of processors is a crucial enabler of many-task computing. Voluntary computing systems have proven that it is possible to build computing plat...