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VEE
2010
ACM
327views Virtualization» more  VEE 2010»
14 years 8 days ago
AASH: an asymmetry-aware scheduler for hypervisors
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
Vahid Kazempour, Ali Kamali, Alexandra Fedorova
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
13 years 12 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
AGI
2008
13 years 6 months ago
Engineering Utopia
The likely advent of AGI and the long-established trend of improving computational hardware promise a dual revolution in coming decades: machines which are both more intelligent an...
J. Storrs Hall
AOSD
2010
ACM
14 years 4 days ago
Execution levels for aspect-oriented programming
In aspect-oriented programming languages, advice evaluation is usually considered as part of the base program evaluation. This is also the case for certain pointcuts, such as if p...
Éric Tanter
ICFP
2009
ACM
14 years 6 months ago
A concurrent ML library in concurrent Haskell
rrent ML, synchronization abstractions can be defined and passed as values, much like functions in ML. This mechanism admits a powerful, modular style of concurrent programming, c...
Avik Chaudhuri