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» The Sensitivity of Communication Mechanisms to Bandwidth and...
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HPCA
2007
IEEE
14 years 5 months ago
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...
Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. ...
CORR
2004
Springer
148views Education» more  CORR 2004»
13 years 5 months ago
Supporting Bandwidth Guarantee and Mobility for Real-Time Applications on Wireless LANs
The proliferation of IEEE 802.11-based wireless LANs opens up avenues for creation of several tetherless and mobility oriented services. Most of these services, like voice over WL...
Srikant Sharma, Kartik Gopalan, Ningning Zhu, Gang...
ICPP
1999
IEEE
13 years 9 months ago
A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting
This paper presents a mesh with virtual buses as the bandwidth-efficient implementation of the mesh with multiple broadcasting on which many computational problems can be solved w...
Jong Hyuk Choi, Bong Wan Kim, Kyu Ho Park, Kwang-I...
CF
2010
ACM
13 years 10 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
SIGMETRICS
2012
ACM
247views Hardware» more  SIGMETRICS 2012»
11 years 7 months ago
A scalable architecture for maintaining packet latency measurements
Latency has become an important metric for network monitoring since the emergence of new latency-sensitive applications (e.g., algorithmic trading and high-performance computing)....
Myungjin Lee, Nick G. Duffield, Ramana Rao Kompell...