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» The Size and Depth of Layered Boolean Circuits
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DAC
1996
ACM
13 years 10 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl
COLT
2008
Springer
13 years 7 months ago
Learning Acyclic Probabilistic Circuits Using Test Paths
We define a model of learning probabilistic acyclic circuits using value injection queries, in which an arbitrary subset of wires is set to fixed values, and the value on the sing...
Dana Angluin, James Aspnes, Jiang Chen, David Eise...
CSR
2010
Springer
13 years 10 months ago
Balancing Bounded Treewidth Circuits
Algorithmic tools for graphs of small treewidth are used to address questions in complexity theory. For both arithmetic and Boolean circuits, it is shown that any circuit of size ...
Maurice Jansen, Jayalal M. N. Sarma
SPAA
2005
ACM
13 years 11 months ago
Parallelizing time with polynomial circuits
We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...
Ryan Williams
TCS
1998
13 years 5 months ago
Threshold Dominating Sets and an Improved Characterization of W[2]
The Threshold Dominating Set problem is that of determining for a graph G = (V, E) whether there is a subset V ⊆ V of size k, such that for each vertex v ∈ V there are at leas...
Rodney G. Downey, Michael R. Fellows