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» The behavior of linear time invariant RLC circuits
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CDC
2010
IEEE
165views Control Systems» more  CDC 2010»
12 years 11 months ago
The behavior of linear time invariant RLC circuits
It is shown that just as we did for a purely resistive network [10], that circuit analysis is very simple if the elements are described not by potentials across and currents throug...
Erik I. Verriest, Jan C. Willems
ICCAD
2003
IEEE
161views Hardware» more  ICCAD 2003»
14 years 1 months ago
A General S-Domain Hierarchical Network Reduction Algorithm
This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexi...
Sheldon X.-D. Tan
DATE
2007
IEEE
126views Hardware» more  DATE 2007»
13 years 10 months ago
WAVSTAN: waveform based variational static timing analysis
— We present a waveform based variational static timing analysis methodology. It is a timing paradigm that lies midway between convention static delay approximations and full dyn...
Saurabh K. Tiwary, Joel R. Phillips
TCAD
2002
99views more  TCAD 2002»
13 years 4 months ago
Analysis of on-chip inductance effects for distributed RLC interconnects
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
Kaustav Banerjee, Amit Mehrotra
ASPDAC
2004
ACM
144views Hardware» more  ASPDAC 2004»
13 years 8 months ago
Verification of timed circuits with symbolic delays
When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the ve...
Robert Clarisó, Jordi Cortadella