Sciweavers

17 search results - page 1 / 4
» The design, implementation, and evaluation of a compiler alg...
Sort
View
PLDI
2003
ACM
13 years 9 months ago
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
This paper presents the design and implementation of a compiler algorithm that effectively optimizes programs for energy usage using dynamic voltage scaling (DVS). The algorithm ...
Chung-Hsing Hsu, Ulrich Kremer
LCPC
2005
Springer
13 years 9 months ago
Interprocedural Symbolic Range Propagation for Optimizing Compilers
Abstract. We have designed and implemented an interprocedural algorithm to analyze symbolic value ranges that can be assumed by variables at any given point in a program. Our algor...
Hansang Bae, Rudolf Eigenmann
MM
2004
ACM
109views Multimedia» more  MM 2004»
13 years 9 months ago
Practical voltage scaling for mobile multimedia devices
This paper presents the design, implementation, and evaluation of a practical voltage scaling (PDVS) algorithm for mobile devices primarily running multimedia applications. PDVS s...
Wanghong Yuan, Klara Nahrstedt
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 4 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
DAC
2005
ACM
14 years 5 months ago
User-perceived latency driven voltage scaling for interactive applications
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
Le Yan, Lin Zhong, Niraj K. Jha